-- clock process
	process
	begin
		clk <= '0';
		wait for 10ns;
		for i in 1 to 80 loop
			clk <= not clk;
			wait for 5ns;
		end loop;
		wait;
	end process;

   -- Stimulus process
   process
   begin		
      rst <= '1';
		
		-- PC = 00, LDI  9E
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 5ns; rst <= '0'; wait for 6ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_load;
		data <= "10011110"; wait for 10ns;
		
		-- PC = 02, ADDI AA (A = 48, C=1)
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_add;
		data <= "10101010"; wait for 10ns;

		-- PC = 04, STO  3F
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111111"; wait for 10ns;
		-- data should be "01001000"
		rd <= '0'; wr <= '1'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "ZZZZZZZZ"; wait for 5ns;
		assert data = "01001000" report "incorrect data value"; wait for 5ns;

		-- PC = 06, ADC  3F (A = 91, C = 0)
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111111"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_addc;
		data <= "01001000"; wait for 10ns;

		-- PC = 08, STO  3F
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111111"; wait for 10ns;
		-- data should be "10010001"
		rd <= '0'; wr <= '1'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "ZZZZZZZZ"; wait for 5ns; 
		assert data = "10010001" report "incorrect data value"; wait for 5ns;

		-- PC = 0A ADCI 7B (A = 0C, C = 1)
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_addc;
		data <= "01111011"; wait for 10ns;

		-- PC = 0C, XOR  3F (A = 9D, C = 1)
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111111"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_xor;
		data <= "10010001"; wait for 10ns;

		-- PC = 0E, ADCI 4A (A = E8, C = 0)
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_addc;
		data <= "01001010"; wait for 10ns;

		-- PC = 10, STO  3E
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111110"; wait for 10ns;
		-- data should be "11101000"
		rd <= '0'; wr <= '1'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "ZZZZZZZZ"; wait for 5ns; 
		assert data = "11101000" report "incorrect data value"; wait for 5ns;

		-- PC = 12, LD   3F
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111111"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_load;
		data <= "10010001"; wait for 10ns;

		-- PC = 14, XORI FF
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_xor;
		data <= "11111111"; wait for 10ns;

		-- PC = 16, ADD  3E (C =1)
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111110"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_add;
		data <= "11101000"; wait for 10ns;

		-- PC = 18, JC   28
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '0'; ld_pc <= '1'; ld_mar <= '0'; op <= my_hold;
		data <= "00101000"; wait for 5ns;
		assert address = x"19" report "incorrect address value"; wait for 5ns;

		-- PC = 28, ADDI 01
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_add;
		data <= "00000001"; wait for 5ns;
		assert address = x"29" report "incorrect address value"; wait for 5ns;

		-- PC = 2A, STO 3E
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '1'; op <= my_hold;
		data <= "00111110"; wait for 10ns;
		-- data should be 57
		rd <= '0'; wr <= '1'; fetch <= '0'; inc_pc <= '0'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "ZZZZZZZZ"; wait for 5ns;
		assert data = "01010111" report "incorrect data value"; wait for 5ns;

		-- PC = 2C, JMP 12
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 10ns;
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '1'; ld_mar <= '0'; op <= my_hold;
		data <= "00010010"; wait for 10ns;

		-- PC = 12
		rd <= '1'; wr <= '0'; fetch <= '1'; inc_pc <= '1'; ld_pc <= '0'; ld_mar <= '0'; op <= my_hold;
		data <= "XXXXXXXX"; wait for 5ns;
		assert address = x"12" report "incorrect address value"; wait for 5ns;
      wait;
   end process;